Xilinx Design Summary

LRIT Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	78	2,400	3%
Number of 4 input LUTs	72	2,400	3%
Logic Distribution
Number of occupied Slices	76	1,200	6%
Number of Slices containing only related logic	76	76	100%
Number of Slices containing unrelated logic	0	76	0%
Total Number 4 input LUTs	94	2,400	3%
Number used as logic	72
Number used as a route-thru	22
Number of bonded IOBs	15	140	10%
IOB Flip Flops	3
Number of GCLKs	1	4	25%
Number of GCLKIOBs	1	4	25%
Total equivalent gate count for design	1,245
Additional JTAG gate count for IOBs	768

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met